1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device and to a method for manufacturing a semiconductor device, and more particularly, to a memory device and a method for manufacturing the memory device including a resistance change layer as a storage node.
2. Description of the Related Art
Consumer demand for highly integrated semiconductor devices has led to the miniaturization of a unit cell of a memory device. The miniaturization (e.g., scaling-down of a unit cell size) of a memory device may be closely related to the manufacturing process used for making the memory device(s). Therefore, one approach to reduce the size of a memory device may be to improve the manufacturing process for making the memory device(s).
Among various device elements that may constitute a unit cell of a memory device, scaling down the size of a device element in which a bit data may actually be written (for instance, a capacitor in the case of a dynamic random access memory device (DRAM) and/or a static random access memory device (SRAM) and, a magnetic tunnel junction (MTJ) cell in the case of a magnetic random access memory device (MRAM)) may be one method to advance the miniaturization in size of a memory device.
In an attempt to advance the size reduction, a memory device using a resistance change layer as a storage node may be used. Hereinafter, this type of memory device will be referred to as a “conventional memory device.”
The following discussion of the embodiments of FIGS. 1-14 relates to conventional method(s) of forming conventional memory devices. FIG. 1 is a diagram showing a cell array of a conventional memory device. In FIG. 1, reference numerals 2, 4 and 6 may represent a word line, a resistance change cell and a bit line, respectively. Also, reference notation C may represent a unit memory cell including the word line 2, the bit line 6 and one resistance change cell 4. As illustrated in FIG. 1, each of the word lines 2 perpendicularly cross each of the bit lines 6, and at these crossing points, the resistance change cells 4 are inserted individually between the word line 2 and the bit line 6.
As noted, FIGS. 2 through 14 are diagrams illustrating a method of manufacturing a conventional memory device including the cell array as shown in FIG. 1.
Referring to FIG. 2, n+-type conductive impurities may be doped on a silicon-on-insulator (SOI) substrate A1 including a silicon substrate 10, a silicon oxide layer 12 and a first silicon layer 13 which may be sequentially stacked. At this time, the doping may be targeted on the first silicon layer 13, and the dose may be controlled to be greater than about 1020/cm3. Reference numeral 14 in FIG. 3 may represent an impurity doped silicon layer of the SOI substrate A1 which may be obtained by the above-described doping process. Also, in FIGS. 2 and 3, the diagrams shown on the right side correspond to the diagrams shown on the left side, respectively. This specific corresponding arrangement of the diagrams is also applied to FIGS. 4 through 14. Particularly, in FIGS. 2-14, the diagram on the left is a cross-sectional view taken along a first plane and the diagram on the right is another cross-sectional view taken along a second plane orthogonally (e.g., at 90°) intersecting the first plane of a conventional memory device as described below.
Referring to FIG. 4, a second silicon layer 16 may be formed on the impurity doped silicon layer 14 through (for example) an epitaxial growth method. Then, n+-type impurity doping may be conducted on the second silicon layer 16, thereby forming an n+-type doping layer 16a as a bottom layer of the second silicon layer 16. FIG. 5 shows this n+-type doping layer 16a. 
Next, referring to FIG. 5, p-type conductive impurities may be implanted onto the second silicon layer 16. As illustrated in FIG. 6, as a result of this ion implantation, a p-type doping layer 16b may be formed as a top layer of the second silicon layer 16. Through these sequential process steps, the second silicon layer 16 may become a PN junction layer, that is, a diode layer.
Referring to FIG. 7, a resistance change layer 18 may be formed on the second silicon layer 16. Although not illustrated, a photoresist layer may be formed on the resistance change layer 18 and may then be patterned in the form of a strip. See diagram on left side of FIG. 8. Afterwards, the resistance change layer 18, the second silicon layer 16 and the impurity doped silicon layer 14 may be sequentially etched by using (for example) a photoresist pattern as an etch mask. This etching may continue until the silicon oxide layer 12 may be exposed. See diagram on left side of FIG. 8. After the etching, the photoresist pattern may be removed. Through this etching, as shown in the diagram on the left side of FIG. 8, the resistance change layer 18, the second silicon layer 16 and the impurity doped silicon layer 14 may be patterned in the form of a strip. The patterned impurity doped silicon layer 14 may be used as a word line. Note that in FIG. 8, the diagram on the left side is a cross-sectional view taken along line 8-8′ of the structure of FIG. 9, while the diagram on the right side is a cross-sectional view of the same structure taken along line 8b-8b′ of FIG. 9. Stated differently, the first plane along line 8-8′ is perpendicular to the second plane along line 8b-8b′.
FIG. 9 is a perspective view showing the above resulting substrate structure after the etching process. In particular, FIG. 9 clearly shows the change in the shape of the impurity doped silicon layer 14, the second silicon layer 16 and the resistance change layer 18 that may be made via the above-described etching process.
Referring to FIG. 10, after the etching process, a first interlayer insulating layer 22 may be formed on the exposed silicon oxide layer 12, covering patterned structures each including the patterned resistance change layer 18, the patterned second silicon layer 16 (16a and 16b) and the patterned impurity doped silicon layer 14. Subsequently, as shown in FIG. 11, the first interlayer insulating layer 22 may be planarized (removed) until a surface of the patterned resistance change layer 18 may be exposed. After the planarization process, the first interlayer insulating layer 22 may remain only at spaces 20, each present between the patterned structures. Also, the planarization process may cause (or lead to) the first interlayer insulating layer 22 to insulate the patterned structures from each other.
Referring to FIG. 12, a conductive layer 24 may be formed on the planarized first interlayer insulating layer 22 and the patterned resistance change layer 18. The conductive layer 24 may be used for forming bit lines.
To form bit lines perpendicular to the patterned impurity doped silicon layer 14, which may be used as a word line, the conductive layer 24 may be etched in the form of strips perpendicular to the patterned impurity doped silicon layer 14. This perpendicular orientation is illustrated on the right-side diagram of FIG. 13. This etching process may be used not only for etching the conductive layer 24 in the form of strips, but also for forming the patterned second silicon layer 16 and the patterned resistance change layer 18 as a part of a unit cell to obtain the cell array shown in FIG. 1. Hence, the etching process with respect to the conductive layer 24 may be performed not only until the patterned impurity doped silicon layer 14 may be exposed, but until the silicon oxide layer 12 may be exposed to yield the pattern shown in FIG. 13. Note that as shown in the diagram on the left side of FIG. 13, the patterned impurity doped silicon layer 14 may be etched down to the top of the silicon dioxide layer 12; whereas, as shown in the diagram on the right side of FIG. 13, the patterned impurity doped layer 14 remains intact above the silicon oxide layer 12. Through this etching process, the conductive layer 24 may be patterned in the form of strips, that is, the bit lines (e.g., of layer 24) may be formed in a perpendicular orientation to the patterned impurity doped silicon layer 14. Also, the patterned second silicon layer 16 and the patterned resistance change layer 18 may exist at a region where the patterned impurity doped silicon layer 14 and the patterned conductive layer 24 may make contact with each other. In other words, layers 16 and 18 may be sandwiched between layers 14 and 24 as shown.
Referring to FIG. 14, a second interlayer insulating layer 26 may be formed over the patterned conductive layer 24 by filling spaces created between the patterned conductive layer 24 as shown. Through these sequential processes, the cell array shown in FIG. 1 may be completely formed.
The conventional memory device manufactured through the above-described manufacturing method may use the resistance change layer for writing bit data. Although this use of the resistance change layer may improve the miniaturization of a memory device, this above-described conventional method (of FIGS. 1-14) may still have difficulty in scaling down the unit cell size to less than about 4F2 (F=45 nm).